To improve the reliability of a memory, an ECC (Error Correcting Code) or a parity bit may be added to payload data.
Usually, a memory element is added in a width direction (a horizontal ECC or a horizontal parity) specifically for the added ECC or parity bit.
For example, a memory with a special ×9-bit configuration may be used instead of a memory with a ×8-bit configuration.
However, it is often the case that addition of a memory element or use of a special memory is disadvantageous in cost and leads to difficulty in availability of parts.
As one of solutions, a vertical ECC or a vertical parity (to be described hereinafter as the vertical ECC) may be used, according to which the ECC is stored in a depth direction instead of the width direction, thus eliminating the need for expanding the memory in the width direction.
For example, suppose that the ECC is added according to a vertical ECC method to a memory configuration as illustrated in FIG. 1.
In FIG. 1, four pieces of payload data, each having a data width of 1 byte, are stored in one address.
In the memory configuration of FIG. 1, when 1 byte of the ECC is added for every 4 bytes of payload data according to the vertical ECC, this results in an arrangement of data as illustrated in FIG. 2.
In reading from successive addresses in the memory using the vertical ECC, data of a second read from the memory (second data) is also used in a subsequent read from a succeeding address when the ECC is included.
In a case where a request source of read requests manages the payload data in the arrangement of data of FIG. 1, and the memory manages the payload data and the ECC in the arrangement of data of FIG. 2, when there is a read request for the data of address 0000h of FIG. 1 (D0 through D3), the following data reads are performed.
The data of address 0000h (D0 through D3) and then the data of address 0004h (ECC0 through D6) of FIG. 2 are read out from the memory. Error correction is performed using ECC0 on D0 through D3 that have been read out, and error-corrected D0 through D3 are outputted to the request source.
Further, when there is a read request for the data of address 0004h of FIG. 1 (D4 through D7), the following data reads are performed.
The data of address 0004h (ECC0 through D6) and then the data of address 0008h (D7 through D9) of FIG. 2 are read out from the memory. Error correction is performed using ECC1 on D4 through D7 that have been read out, and error-corrected D4 through D7 are outputted to the request source.
As described above, when the addresses to be read are successive, the second data (in the above example, the data of address 0004h of FIG. 2) needs to be read twice from the memory.
However, it is often the case that a memory access involves an overhead (for example, in DRAM (Dynamic Random Access Memory), operating on the same bank generates a period of inaccessibility). Reading the second data twice causes a loss of performance and is thus inefficient.
Electrical power is consumed in every memory access, so that reading the second data twice results in increased electrical power consumption.
As a technique for data transfer involving a parity check result, there is a technique in which bus control is implemented in successive accesses such that the next read request is not accepted before a parity check result is outputted, thus putting the read request on hold until data transfer after a parity check (for example, Patent Literature 1).